1. Field of the Invention
The present invention generally relates to single chip implementations of logic and memory components and, more particularly to a method for system-on-chip layout automation which translates (compiles) a hardware description language (HDL) of a design, consisting of logic components and memory components, into a layout on a silicon chip, with optimized floor plan, macro and layout structures of logic and dynamic random access memory (DRAM) circuits.
2. Background Description
The performance gap, which is the difference between the processor's computation rate (e.g., measured in MIPS or millions of instructions per second), and the memory's access data rate, exhibited in today's microprocessor and main memory, is becoming larger and larger for each new generation of chips. The bandwidth bottleneck between the graphics controller (processor) and frame buffer (memory) limit the performance of the conventional display subsystems.
The main reason of the above problems in systems with processor and dynamic random access memory (DRAM) is due to the fact that processor chips and memory chips are implemented in separate chips. There are other attempts to solve the problems, namely by using multi-layer ceramic module (MCM) technology or silicon on insulator (SOI) carrier technology to house the individual silicon chips together. But this still does not address the problem that the processors (logic) and the memory (DRAM) are implemented in different chips and, as a result, the limited bandwidth between the processor and the memory and the large capacitive loads presented In the off-chip interconnections are still limiting the overall system performance.